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Presentation
Building Better IP with RTL Architect NoC IP Physical Exploration
Voted one of the “Top Ten Best Presentations” at SNUG Silicon Valley 2023, this presentation discusses the importance of NoCs and their impact on timing analysis and power consumption. It introduces a flow and methodology that utilizes RTL-based estimation of timing and power consumption using RTL Architect in conjunction with Arteris’ FlexNoC 5 and Ncore NoC development frameworks. FlexNoC 5 facilitates up to 5X faster physical convergence of the back-end physical design time and effort.
Presentation
FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)
Failure modes, effects, and diagnostic analysis (FMEDA) for sophisticated chips with hundreds of IP blocks are fraught with complexity and opportunities for systematic errors. This presentation will describe an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics.
Presentation
Is the Missing Safety Ingredient in Automotive AI Traceability?
Presented at The Linley Spring Processor Conference 2022, describes the importance of traceability as it applies to managing SoC requirements and customer deliverables whilst also shortening the path to functional safety certification including ISO 26262.
Presentation
Safety Considerations for Network-on-Chip (NoC) Development
This presentation illustrates functional safety challenges in system design and adherence to the ISO 26262 standard for automotive electronics. It highlights Network-on-Chip (NoC) safety mechanisms, including timeouts, IP Block isolation, and end-to-end interface protection.
Presentation
The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems
Discover how networks-on-chips (NoCs) are revolutionizing AI/ML across sensors, edge devices, and data centers. This video presentation explores how NoCs enable rapid data movement, seamless component integration, and efficient chip-to-chip communication, paving the way for a new era of AI-powered devices.
Podcast
EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling
In this podcast with Amelia Dalton and Andy Nightingale, explore the key challenge faced by SoC designers when building NoC interconnects for AI-based designs, the details of NoC interconnect IP soft tiling, and some real-world examples of AI-based designs that benefit from NoC IP soft tiling.
Podcast
EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
Physically aware network-on-chips take center stage in this week’s Fish Fry podcast! Andy Nightingale from Arteris and I investigate the role that network-on-chips have played in the development of SoC designs.
Podcast
Electronic Design: All About NoCs
Today’s SoCs are very complex. They have multiple cores and often these cores vary in type, e.g., CPUs, GPUs, and NPUs. Connecting these to peripherals and memory typically involves one or more network-on-chips (NoCs). In this podcast, Electronic Design Editor Bill Wong talks with Andy Nightingale, VP Product Management and Marketing at Arteris, about NoCs.
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