解决多核设计挑战并且提供安全支持
开发多核 ASIC 的关键挑战包括管理复杂性、功耗优化、核间通信、同步、验证、测试和性能优化,同时确保可扩展性、可靠性和集成的简易性。
Ncore™ 通过提供经量产验证过、高度可配置且高效的一致 NoC 互连 IP 解决方案来解决这些挑战,该解决方案可与多种协议和包括 Arm 和 RISC-V 在内的任何处理器配合使用。Ncore 经过精心设计,支持 ISO 26262 设计,从而提供了独特的价值,一旦获得认证,将确保在符合功能安全要求的安全关键型应用中可靠运行。
在 ASIC 设计中结合使用 Ncore IP 和 FlexNoC IP 可实现无与伦比的性能优化、可扩展性和系统集成,实现强大的缓存一致性、高效通信和灵活性,从而实现市场差异化并加快产品上市时间。
唯一的多协议 AMBA CHI-B、CHI-E 和 ACE 缓存一致性 NoC
帮助 SoC 开发人员创建高性能一致性SoC
可扩展
Ncore 提供高带宽、低延迟的互连结构,实现 SoC 不同组件之间的高效通信,提供从小型嵌入式系统到大型数十亿晶体管设计的可扩展性能和功耗效率。
可配置
多种一致性协议的支持能为已有的和未来的 IP 提供更多选择和复用的机会。连接到同一个 Ncore上的,发起传输的IP 可以遵守的是不同的一致性协议,包括(CHI-E、CHI-B 和 ACE 以及 ACE-Lite IO )。Ncore 还允许 AXI 非一致性代理充当 IO 一致性代理。
安全
通过外部评估员的 ISO 认证,确保 Ncore 可用于符合 ISO 26262 标准的芯片,根据安全性和可靠性产品选项,可提供的 ASIL B 到 ASIL D 要求。
Ncore 主要功能
- 高度可扩展的系统
- 真正的异构一致性
- 可配置网络和拓扑
- 可配置的探听过滤器
- IO缓存和系统内存缓存
- 更低功耗
- 功能安全
- 服务质量 (QoS)
- 调试和跟踪/监控
Ncore 产品优势
频率高,延迟时间短
使用多个可配置的探听过滤器来适应不同的缓存组织
低功耗
减少片外主存访问,从而降低功耗
较小的芯片面积
使用最佳 NoC 传输层减少线路
配置简单
Ncore 适应每个一致性代理的行为和特征
自动验证
通过自动生成验证,可以节省数百个小时的工时
缩短项目周期
更少的迭代循环
访问我们的 NoC Technology页面了解更多
We are happy to share that we are partnering with Arteris to use Ncore and FlexNoC IP in our next-generation product. The combination of performance and features made it a great choice for both our AI chips and our high-performance RISC-V CPUs. The Arteris team and IP solved our on-chip network problems so we can focus on building our next-generation AI and RISC-V CPU products.
Tenstorrent – Ncore
Jim Keller, CEO, TenstorrentWe chose the Arteris Ncore cache coherent interconnect because of its unique proxy caches and their ability to underpin high-performance, low power, cache coherent clusters of our unique AI accelerators. And with our prior experience using FlexNoC and the FlexNoC FuSa Option for functional safety, we trust Arteris to be the highest performing and safest choice for ISO 26262-compliant NoC IP.
Mobileye
Elchanan Rushinek, Vice President of Engineering, MobileyeWe are excited to partner with Arteris to accelerate the creation and delivery of an advanced communication SoC. Now, we can focus our resources where we bring the most value. Our company will leverage Arteris’ proven Ncore and FlexNoC technology and interconnect expertise for a combination that allows us to provide our customers with the best products in the shortest amount of time.
SCALINX – Ncore
Hussein Fakhoury, CEO of SCALINXArteris NoC technology enables wide on-chip bandwidth with fewer wires and lower latency than traditional bus and crossbar fabrics. This multiuse deal is expected to help us deliver these benefits more quickly to engineering teams throughout Freescale.
Freescale
Fares Bagh, Vice President of R&D, FreescaleWe have worked with Arteris NoC technology since 2010, and are excited that Arteris has brought its significant engineering prowess to help solve the problems of fault tolerant and reliable SoC design.
Mobileye
Elchanan Rushinek, Vice President of Engineering, Mobileye- Articles
- Cache Coherency In Heterogeneous Systems | Semiconductor Engineering
- SoC design: When a network-on-chip meets cache coherency | EDN
- Optimizing Communication and Data Sharing in Multi-Core SoC Designs | Design & Reuse
- Press Releases
- Arteris Expands Ncore Cache Coherent Interconnect IP To Accelerate Leading-Edge Electronics Designs | Mar 13, 2024
- Arteris Ncore Cache Coherent Interconnect IP Certified for ISO 26262 Automotive Functional Safety Standard | Nov 14, 2023
- Arteris Wins Autonomous Vehicle Technology of the Year Award | Oct 05, 2023
- Technical Papers
- Customers
- SCALINX and Arteris Partner on Advanced Communications Innovation | Dec 12, 2023
- Tenstorrent Selects Arteris IP for AI High-Performance Computing and Datacenter RISC-V Chiplets | May 02, 2023
- Ncore Licensed by Bitmain for Sophon TPU Artificial Intelligence (AI) Chips | July 09, 2019
- Ncore Implemented in Toshiba ISO 26262-Compliant ADAS Chip | June 11, 2019
- Ncore is Implemented by NXP | May 24, 2016
- Ecosystem
- Arteris Expands Automotive Solutions for Armv9 Architecture CPUs | Mar 13, 2024
- Semidynamics and Arteris Partner To Accelerate AI RISC-V System-on-Chip Development | Nov 02, 2023
- Fraunhofer IESE Partners With Arteris To Accelerate Advanced Network-on-chip Architecture Development for AI/ML Applications | Oct 17, 2023
- Arteris and SiFive Partner to Accelerate RISC-V SoC Design of Edge AI Applications | Feb 27, 2023
- Expanded Partnership Between Arteris and Arm to Accelerate Automotive Electronics | Sep 12, 2022
- Synopsys Delivers Industry’s First Cache Coherent Subsystem Verification Solution for Arteris Ncore Interconnect | May 24, 2016
- Industry Support for the Synopsys ARC-V Processor IP Portfolio
- Webinars