安全支持下的多核设计挑战解决方案
Arteris凭借其扩展的multi-die互连解决方案,加速AI驱动的芯片创新。经过硅验证的片上一致性互连IP核Ncore™,现已实现芯粒间全缓存一致性,为设计人员提供快速模块化创新的基础技术。
基于十余年量产芯片验证,Ncore™具备高度可配置性、超低功耗特性,兼容包括Arm®和RISC-V在内的所有处理器架构。
该方案符合ISO 26262 ASIL D功能安全等级要求,并与Magillem™ IP集成自动化软件协同工作,助力开发团队快速扩展模块化架构、简化多芯片设计流程、大幅缩短开发周期。
Ncore与FlexNoC协同工作,可提供无与伦比的性能优化能力、可扩展性和系统集成度,实现强大的缓存一致性、高效通信和设计灵活性,从而在单芯片或跨芯粒架构中打造差异化市场优势,并显著加速产品上市进程。
唯一的多协议 AMBA CHI-B、CHI-E 和 ACE 缓存一致性 NoC
帮助 SoC 开发人员创建高性能一致性SoC
可扩展
Ncore 提供了一个高带宽、低延迟的互连架构,用于实现 SoC 不同组件之间以及多个芯片之间的高效通信,从而为从小型嵌入式系统到大型数十亿晶体管和 multi-die 设计提供可扩展的性能和功耗效率。
可配置
多协议一致性为传统和未来的IP支持提供了选择和重用性。 CHI-E、CHI-B和ACE一致性以及ACE-Lite I/O一致性代理接口允许多个发起方IP连接到同一个Ncore。 Ncore还允许AXI非一致性代理作为I/O一致性代理运行。
安全
通过外部评估机构的ISO认证,确保Ncore已为用于符合ISO 26262标准的芯片做好准备,涵盖ASIL B至ASIL D等级,该功能由Ncore安全与可靠性产品选项启用。 自动生成您的Ncore配置的故障模式、影响和诊断分析 (FMEDA) 数据。
Ncore 主要功能
- 高度可扩展的系统
- 真正的异构一致性支持,可混合使用AMBA CHI和AMBA ACE协议
- 完整支持缓存处理器一致性及加速器I/O一致性
- 通过AMBA CXS.B接口实现基于UCIe™ 1.1的多芯片缓存一致性*,最多支持4个芯粒,并且每个芯片最多支持4个64 GB/s的链路*
- 可配置网络及拓扑结构
- 采用物理分块重复的网状拓扑结构*
- 具有重复块物理平铺的网格拓扑结构*
- 具备FMEDA生成和ASIL D认证的功能安全*
- 可配置探听过滤器
- I/O代理缓存与系统内存缓存
- 低功耗设计
- 服务质量(QoS)保障
- 调试与追踪/监控功能
注:带*号标记为可选配置项
探索 Ncore 的更多功能,下载产品手册
特点
NoC 瓦格化(tiling)- Ncore 的新功能
在网格拓扑中,瓦格化可以支持到256个 CPU 分布到32个簇中
- 性能扩展
- 缩短设计时间
- 速度测试
- 减少设计风险
- 支持 Arm 和 RISC-V 架构
创建模块化、可扩展的设计,实现更快的集成、验证和优化。
Ncore 产品优势
频率高,延迟时间短
使用多个可配置的探听过滤器来适应不同的缓存组织
低功耗
减少片外主存访问,从而降低功耗
较小的芯片面积
使用最佳 NoC 传输层减少线路
配置简单
Ncore 适应每个一致性代理的行为和特征
更快的上市
瓦格化(tiling)加速物理设计、实现和时序闭合
灵活的拓扑
可选择crossbar、网格和ad-hoc拓扑
安全
自动化FMEDA安全文档,符合ISO26262 ASIL B到D认证
自动验证
通过自动生成验证,可以节省数百个小时的工时
缩短项目周期
更少的迭代循环
访问我们的 NoC Technology页面了解更多
精选解决方案
基于芯粒设计的核心技术基石
- 灵活的可扩展设计
- 差异化的 AI 性能优势
- 符合持续演进的行业标准
依托经过硅验证的NoC IP和Magillem™自动化技术,实现模块化架构扩展、简化multi-die项目流程,并大幅缩短开发周期。
We are happy to share that we are partnering with Arteris to use Ncore and FlexNoC IP in our next-generation product. The combination of performance and features made it a great choice for both our AI chips and our high-performance RISC-V CPUs. The Arteris team and IP solved our on-chip network problems so we can focus on building our next-generation AI and RISC-V CPU products.
Tenstorrent – Ncore
Jim Keller, CEO, Tenstorrent
We chose the Arteris Ncore cache coherent interconnect because of its unique proxy caches and their ability to underpin high-performance, low power, cache coherent clusters of our unique AI accelerators. And with our prior experience using FlexNoC and the FlexNoC FuSa Option for functional safety, we trust Arteris to be the highest performing and safest choice for ISO 26262-compliant NoC IP.
Mobileye
Elchanan Rushinek, Vice President of Engineering, MobileyeWe are excited to partner with Arteris to accelerate the creation and delivery of an advanced communication SoC. Now, we can focus our resources where we bring the most value. Our company will leverage Arteris’ proven Ncore and FlexNoC technology and interconnect expertise for a combination that allows us to provide our customers with the best products in the shortest amount of time.
SCALINX – Ncore
Hussein Fakhoury, CEO of SCALINX
Arteris NoC technology enables wide on-chip bandwidth with fewer wires and lower latency than traditional bus and crossbar fabrics. This multiuse deal is expected to help us deliver these benefits more quickly to engineering teams throughout Freescale.
Freescale
Fares Bagh, Vice President of R&D, Freescale
We have worked with Arteris NoC technology since 2010, and are excited that Arteris has brought its significant engineering prowess to help solve the problems of fault tolerant and reliable SoC design.
Mobileye
Elchanan Rushinek, Vice President of Engineering, Mobileye- Articles
- Reducing SoC Power With NoCs And Caches | Semiconductor Engineering
- Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning | Design & Reuse
- Why NoC tiling matters in AI-centric SoC designs | EDN
- Cache Coherency In Heterogeneous Systems | Semiconductor Engineering
- SoC design: When a network-on-chip meets cache coherency | EDN
- Optimizing Communication and Data Sharing in Multi-Core SoC Designs | Design & Reuse
- Press Releases
- Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge AI | Nov 12, 2024
- Arteris Network-on-Chip Tiling Innovation Accelerates Semiconductor Designs for AI Applications | Oct 15, 2024
- Arteris Expands Ncore Cache Coherent Interconnect IP To Accelerate Leading-Edge Electronics Designs | Mar 13, 2024
- Arteris Ncore Cache Coherent Interconnect IP Certified for ISO 26262 Automotive Functional Safety Standard | Nov 14, 2023
- Arteris Wins Autonomous Vehicle Technology of the Year Award | Oct 05, 2023
- Technical Papers
- Customers
- SCALINX and Arteris Partner on Advanced Communications Innovation | Dec 12, 2023
- Tenstorrent Selects Arteris IP for AI High-Performance Computing and Datacenter RISC-V Chiplets | May 02, 2023
- Ncore Licensed by Bitmain for Sophon TPU Artificial Intelligence (AI) Chips | July 09, 2019
- Ncore Implemented in Toshiba ISO 26262-Compliant ADAS Chip | June 11, 2019
- Ncore is Implemented by NXP | May 24, 2016
- Ecosystem
- Arteris Expands Automotive Solutions for Armv9 Architecture CPUs | Mar 13, 2024
- Semidynamics and Arteris Partner To Accelerate AI RISC-V System-on-Chip Development | Nov 02, 2023
- Fraunhofer IESE Partners With Arteris To Accelerate Advanced Network-on-chip Architecture Development for AI/ML Applications | Oct 17, 2023
- Arteris and SiFive Partner to Accelerate RISC-V SoC Design of Edge AI Applications | Feb 27, 2023
- Expanded Partnership Between Arteris and Arm to Accelerate Automotive Electronics | Sep 12, 2022
- Synopsys Delivers Industry’s First Cache Coherent Subsystem Verification Solution for Arteris Ncore Interconnect | May 24, 2016
- Industry Support for the Synopsys ARC-V Processor IP Portfolio
- Webinars