让SoC开发人员更快地创建物理有效的NoC
全球顶级的半导体设计团队利用全球一流的片上结构作为其芯片的片上通信主干,从而应对增长最快的市场。
最新一代 FlexNoC 5 互连及其集成的兼顾物理感知技术为布局和布线团队提供了更好的起点,同时减少了互连面积和功耗。与手动物理迭代相比,FlexNoC 5 的周转时间缩短了 5 倍。
在 ASIC 设计中结合使用 FlexNoC 和 Ncore IP 可提供无与伦比的性能优化、可扩展性和系统集成,从而实现强大的缓存一致性、高效通信和灵活性,实现市场差异化并加快上市速度。
最完备的片上网络产品
涵盖设计团队所需的一切, 助力更快的创建世界一流的SoC
灵活的拓扑结构
FlexNoC 由简单的基本组件生成,这些组件由一组强大的底层算法和直观的 GUI 组合而成,从而可以构建任何拓扑。
支持从小型到大型 SoC
FlexNoC 通过利用源同步通信和虚拟通道轻松支持芯片内部的长路径。
超大带宽
FlexNoC 通过使能多通道 HBMx 存储器和高带宽数据路径来驱动高性能片上数据流和对片外存储器的访问。
FlexNoC 5 主要功能
- 自动时序收敛辅助
- 在布局规划上直接实现拓扑可视化
- 多时钟/电源/电压域和具有单元级时钟门控的电源管理
- 多协议支持包括 AMBA 5,并且包括通过 QoS实现带宽调节器和限制器
- 针对面积更小的总体优化,例如根据配置的不同,部分NoC组件最高可优化30%
- 本地和用户定义的防火墙安全
- 导入和导出到 Magillem 工具
- 支持AMBA 5,DVM 8.1 (分布式虚拟内存)
- 片上性能监控和调试
- 利用ATB 128b和时间戳进行调试和跟踪
NoC集成自动化流程
基于SoC互连信息的自动化流程:
- 简化流程提高效率
- 利用Magillem checker可更早发现集成错误,提高质量
点击了解更多关于Magillem Connectivity 和 Magillem Registers
FlexNoC 产品优势
频率高,延迟时间短
使用内置的 NoC 性能分析探索工具
低功耗
通过时钟门控,DVFS和GALS提供先进的功耗管理
较小的芯片面积
使用最佳 NoC 传输层技术减少连线数量
快速的时序收敛
早期的物理感知,可以加快收敛速度,避免重新设计
配置简单
直观的FlexNoC 5用户界面
自动验证
与手动验证测试工作台相比,可以节省数百小时的工作时间
缩短项目周期
更少的迭代循环
更高的利润
FlexNoC使设计效率的提高,减少了TTM
访问我们的 NoC Technology页面了解更多
Sondrel has deployed Arteris FlexNoC interconnect IP across several customer SoC projects to great effect. Physical constraints have always been an important issue and are even more important below 16nm geometries. The latest FlexNoC 5 with its physical awareness technology, enables our RTL teams to verify that architectures meet physical constraints and provide a better starting point for our place and route team. We look forward to our continued cooperation with Arteris.
Sondrel
Graham Curren, CEO of SondrelUsing Arteris FlexNoC allows us to reduce development time and manage project risk. FlexNoC’s advanced quality-of-service and debugging features, combined with its multi-protocol support, allow Samsung SUHD TVs to reduce power consumption and die area for complex chips with more than 100 IP interfaces.
Samsung
HaeJoo Jeong, Vice President, Visual Display Business, Samsung ElectronicsFlexNoC interconnect IP allowed us to dramatically increase MCU performance and functionality with no impact on die area while significantly decreasing power consumption.
Renesas
Andreas Papliolios, Director of IoT Silicon, Renesas Electronics AmericaAs a result of our thorough evaluation, we know the Arteris FlexNoC interconnect IP will help us shorten development schedules and increase product performance, while simultaneously decreasing costs due to back-end wire routing congestion and timing closure issues.
Toshiba
Yukihiro Urakawa, Senior Manager, Logic LSI Division of Semiconductor & Storage Products Company, Toshiba CorporationBy incorporating Arteris FlexNoC interconnect IP into our development programs, we are able to streamline our overall design time. This solution also provides us with flexibility to create derivations of our offerings to quickly adapt to changing market needs.
Rambus
Mike Uhler, Vice President, Emerging Solutions Division, RambusTSMC chose to work with Arteris on the interposer based test chip program because its interconnect technology is ideally suited to addressing the SoC wire routing congestion and timing closure challenges. TSMC and Arteris are working together to make it easier for our joint customers to adopt these technologies.
TSMC
Suk Lee, Director of Design Infrastructure Marketing, TSMCOur successful adoption of Arteris FlexNoC fabric IP has been straightforward, allowing us to more quickly architect and implement sophisticated systems-on-chip in less time and with better power consumption and performance.
Freescale
Fares Bagh, Vice President of R&D, Freescale- FlexNoC 5 Datasheet
- Infographic: Accelerating Timing Closure for Networks-on-Chip (NoCs) With Physical Awareness
- Webinar: Arteris FlexNoC 5 – Industry’s First Physically Aware Network-on-Chip IP
- Blogs
- Physically Aware Network-on-Chip Streamlines SoC Design Cycle | Electronic Design
- How Physically Aware Interconnect IP Bolsters SoC Design | EDN
- Considering Semiconductor Implementation Aspects Early During Network-On-Chip Development | Semiconductor Engineering
- Podcast: The Impact of Using a Physically Aware NoC with Charlie Janac | SemiWiki
- Meet the Next-Generation Network-on-Chip From Arteris | Design & Reuse
- Physically Aware NoCs | Semiconductor Engineering
- The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster | EE Journal
- Blogs