Blog

Integrating cache memory into SoCs and IP blocks improves their performance and efficiency. This article highlights technologies and strategies to address challenges like cache coherency and power consumption....

An emphasis on physical awareness significantly reduces the iterative cycles of NoC placement and routing....

Learn about sidestepping data incompatibility issues in heterogeneous chip designs....

SoC design complexity is exploding. CSRCompiler automates hardware/software interface (HSI) tasks, reduces errors, and cuts the HSI development process by up to one-third, minimizing frustration, increasing productivity, reducing risk, and ...

Arteris brings cutting-edge technology to DAC 2024, empowering engineers to create high-performance SoCs with greater efficiency....

Creating a new implementation of an SoC from the ground up is resource-intensive, time-consuming, and expensive. Learn how NoC IP from Arteris was used to bring a derivative design to market faster....