SemiWiki: The Impact of Arteris IP and Its Partnerships on the Automotive Industry and Beyond
Dan explores the impact Arteris is having on high-growth markets such as automotive with Michal. The company’s partnership with Arm is also explored. The impact of Arteris and its
Semiconductor Engineering: Scalability – A Looming Problem In Safety Analysis
A reuse-centric methodology for generating FMEDA.
Semiconductor Engineering: Time For FMEDA Reuse?
How do designers quantify safety in electronic systems? Through one or more tables called Failure Modes, Effects and Diagnostic Analysis – FMEDA.
Semiconductor Engineering: Optimizing NoC-Based Designs
Paul Graykowski at Arteris IP (AIP) writes about switching from crossbar interconnects to NoC to support new breeds of complex SoCs.
Semiconductor Engineering: Where Do Memory Maps Come From?
A memory map is the bridge between a system-on-chip (SoC) and the firmware and software that is executed on it. Engineers may assume the map automatically appears.
SemiWiki: An Ah-Ha Moment for Testbench Assembly
Sometimes we miss the forest for the trees, and I’m as guilty as anyone else. When we think testbenches, we rightly turn to UVM because that’s the agreed standard, and everyone has been investing
EDN: System Architect: Blueprint of a New Job in Semiconductor Industry
According to Isabelle Geday, VP and GM of IP deployment at Arteris IP, the job requires a system-oriented mindset, which calls for a holistic approach to ensure the success of the designed systems.
Semiconductor Engineering: Automotive Outlook: 2022
“Here, initially it was algorithms and AI or machine learning on visual inputs. Then, lidar and radar data was added to that in a sensor fusion function.
EDN: A Closer Look at COVID and the Semiconductor Shortage Saga in 2021
As Arteris IP president and CEO Charlie Janac recalls, there have been shortages before, but not due to such imbalance between new semiconductor-driven applications and business models
Semiconductor Engineering: Industry Transforming In Ways Previously Unimaginable
“Formal can theoretically find every possible bug, but it may take orders of magnitude more time. Formal can be used for unit level, but you often can’t use it on bigger blocks just because the depth to figure out any bug can be too difficult and may take a lifetime to complete. What can be done today, is to use models that represent RTL. In these models, we can abstract out a lot of things that cause depth problems. This can decrease the amount of time it would take to verify the architecture said Chirag Ghandhi, director of verification for…