What the Cyber Resilience Act means for the future of chip design
The EU Cyber Resilience Act is reshaping semiconductor security, making cybersecurity, compliance, and lifecycle management core design priorities.
Semiconductor Engineering: Reducing Avoidable Memory Trips In HBM Systems
As AI and high-performance SoCs increasingly rely on HBM, memory bandwidth alone is no longer enough to maximize performance. This article discusses why the intelligent data movement and cache efficiency are critical to unlocking the full benefits of HBM-based architectures.
Beyond Moore’s Law: Heterogeneous Computing and AI SoCs
As Moore’s Law slows, heterogeneous computing is driving AI, automotive, and data center innovation through specialized compute, chiplets, and advanced interconnects.
EDN: Model your IPs and your NoCs
As SoC and chiplet architectures become increasingly complex, effective modeling must extend beyond functional IP blocks to include the NoC interconnect fabric itself. This article highlights why NoCs have become critical determinants of system performance and explains the value of using consistent transaction-level, cycle-accurate, and RTL models throughout the design flow.
Cyber Defense Magazine: Securing The Unseen Why Data in Motion is the Next Cybersecurity Frontier
Securing the unseen: As AI drives massive data movement inside chips, organizations must secure and monitor data in motion to close hidden hardware attack surfaces.
Achieving ASIL Compliance in Automotive AI Systems
Learn how automotive companies are approaching ASIL compliance for AI systems using safety islands, redundancy, and functional safety architectures.
EE Times: AI-Accelerated Software Security Vulnerability Discovery: Is Hardware Next?
AI is accelerating software vulnerability discovery at unprecedented speed. Could semiconductor hardware be next, and how should the industry prepare?
Semiconductor Engineering: Using SystemC TLM Modeling To Solve AI Data Movement Challenges
SystemC TLM modeling helps AI chip architects analyze NoC data movement early, identify bandwidth and latency bottlenecks, optimize workload behavior, and reduce RTL-stage performance and integration risk. Learn more about how early NoC modeling improves AI system design and accelerates architectural decision-making in the article.
AI-Accelerated Vulnerability Discovery: An Emergency in Software Security. Is Hardware Next?
Frontier AI models are accelerating vulnerability discovery at unprecedented scale, raising urgent questions about the future of hardware security.
EDN: How data movement defines performance for AI silicon
This article explores how AI chip performance is increasingly constrained by data movement rather than raw compute power, highlighting the growing role of network-on-chip (NoC) architectures, chiplets, cache hierarchies, and physically aware design in modern AI SoCs. Learn more about how scalable interconnects, automation, and system-level design approaches help overcome AI-era bottlenecks in the article.