Design & Reuse: Efficient IP Packaging for Today’s SoC Integration
As SoC architectures scale in complexity, managing hundreds of IP blocks consistently from concept through production is critical to avoid costly errors and rework. Standardizing IP descriptions with IEEE 1685 (IP-XACT) and automating packaging ensures interoperability, accelerates design, and promotes reuse across projects. Learn more in the article.
Semiconductor Engineering: A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution
With monolithic SoCs reaching their limits, chiplet-based architectures are key to building flexible, high-performance systems. Arteris’ multi-die solution combines silicon-proven NoC IP, cache coherency, and automation tools to streamline chiplet integration and accelerate time-to-market. Learn more in the article.
RISC-V: Arteris’ Multi-Die Solution for the RISC-V Ecosystem
As AI, HPC, and automotive workloads push past the limits of monolithic SoCs, chiplet-based design offers a scalable and cost-efficient path forward. Arteris enables this shift with advanced NoC IP for coherent and non-coherent multi-die interconnects, UCIe-based die-to-die links, and automation tools for seamless integration. From boosting bandwidth and cache coherency to simplifying system complexity, Arteris delivers the complete solution for next-generation RISC-V processors. Learn more in the article.
Semiconductor Engineering: System Integration With Standards-Based Automation
As SoCs evolve into complex multi-die systems, standards-based automation is key. Learn how IP-XACT and Arteris’ Magillem tools enable consistent metadata, scalable IP reuse, and faster, error-free integration across teams and tools.
EDN: Chiplet design basics for engineers
As AI and HPC workloads intensify, engineers are turning to chiplet-based architectures to overcome the limitations of traditional SoCs. This article explains the fundamentals of chiplet design, its advantages, and the tools enabling scalable, high-performance multi-die systems.
EE Times: Smarter SoC Design for Agile Teams and Tight Deadlines
Advanced NoC automation helps lean SoC teams meet tight deadlines by reducing complexity, cutting design time, and improving power and performance efficiency.
Design & Reuse: Enabling Chiplet Design Through Automation and Integration Solutions
Explore how chiplet-based designs overcome SoC limitations. Arteris’ multi-die solution enables connectivity across chiplets, supporting coherent and non-coherent traffic and intelligent dataflow management.
EDN: Chiplet basics: Separating hype from reality
Planning chiplet-based designs is underway. Yet, uncertainty continues to swirl around chiplet architecture and ready-to-use technologies. New innovations are on the horizon.
Design & Reuse: Automating NoC Design to Tackle Rising SoC Complexity
Modern SoCs typically include between 5 and 20 individual NoC instances, consuming around 10–13% of the total silicon area. However, existing methodologies, especially in light of growing register demands, are proving inadequate. This leads to extended development cycles, frequent design iterations, and heightened schedule risks. To address these challenges, automated NoC generation provides a scalable and efficient solution for managing increasing design complexity. Learn more about how automation is transforming NoC design in this article.
Semiconductor Engineering: CSR Management: Life Beyond Spreadsheets
The hardware-software interface (HSI) that’s physically represented by control and status registers (CSRs) is a critical source of design risk. Mismanagement of CSRs contributes to a number of SoC failures. To avoid these setbacks, engineering teams need a robust, automated approach to CSR definition and management that ensures consistency across hardware and software.