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AI / Machine Learning (9) RISC-V Designs (7) Cybersecurity (6) Hardware Security Assurance (5) ISO 26262 (4) Network-on-Chip IP (4) Traceability (4) FMEDA (3) Functional Safety (3) IP-XACT (3) Magillem Connectivity (3) Multi-Die (3) Network-on-Chip (NoC) (3) FlexGen (2) FlexNoC (2) Magillem Registers (2) Power Consumption (2) Radix-S/M/ST (2) Automotive (1) CodaCache (1) Hardware/Software Interface (HSI) (1) Magillem Packaging (1) Ncore (1) Power Management (1) Routing Congestion (1) SystemC (1)
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Magillem Registers Datasheet
Datasheet

Magillem® Registers

  • A scalable infrastructure that promotes a rapid, highly iterative design environment to specify, document, implement,…
Ncore® Cache Coherent Interconnect Datasheet
Datasheet

Ncore™ Cache Coherent Interconnect IP

  • Cache coherent network-on-chip (NoC) interconnect IP
  • Arm® AMBA® CHI and ACE interoperability
  • ISO 26262-compliant functional safety mechanisms

…

Making Cache Coherent SoC Design Easier with Ncore
White Paper

Making Cache Coherent SoC Design Easier with Ncore™

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris makes cache coherent SoC designs easier, saving 100’s of person-years effort per project vs DIY solutions.
Accelerating Timing Closure for Networks on Chip NoCs With Physical Awareness
Infographic

Accelerating Timing Closure for Networks-on-Chip (NoCs) With Physical Awareness

The number of IP blocks in SoCs and across chiplets continues to grow. See how considering the floorplan information during the NoC architecture, combined with early estimation of pipeline stages can significantly reduce the time to physical closure.
Simplifying SoC Integration with Arteris
Infographic

Simplifying SoC Integration with Arteris

Design teams are getting crushed by complexity. See how to simplify SoC integration with automation, saving engineering cycles and project costs.
Accelerate Time To Market With a First-Time Right Process
Webinar

Accelerate Time To Market With a First-Time Right Process

Explore SoC integration automation with Arteris and see how to boost productivity and meet aggressive schedules despite growing complexity in design.
Arteris FlexNoC 5 - Industry’s First Physically Aware Network-on-Chip IP
Webinar

Arteris FlexNoC 5 – Industry’s First Physically Aware Network-on-Chip IP

Accelerate system-on-chip development with FlexNoC 5 from Arteris, the leading network-on-chip interconnect IP that is used by the top semiconductor and system design teams worldwide. Learn about the latest generation FlexNoC 5 interconnect with its integrated physical awareness technology that gives place and route teams an advanced starting point while simultaneously reducing interconnect area and power consumption.
How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs
Webinar

How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs

Discover how our cache-coherent interconnect solution empowers multi-core SoC design teams, helping them accelerate market entry with high-quality designs and allowing more time for innovation.
Revolutionizing SoC Performance with Network-on-Chip Technology
Webinar

Revolutionizing SoC Performance with Network-on-Chip Technology

See how you can create NoCs with less wires, more bandwidth, smaller area with incredible efficiency, flexibility and scalability to achieve your SoC goals.
Presentation

Tiled Approach to System Scaling

Today’s large-scale SoCs such as AI accelerators often deploy regular repeating arrays of processor elements. See how tiling accelerates physical design by enabling re-use of hardened physical blocks in addition to logical elements.
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