Generic selectors
Exact matches only
Search in title
Search in content
Post Type Selectors

Resources Search

background-element-24

Sort & Filter

Type
Resources catergories filter
Resources Type Filter
Year filter
Show More
Latest
Oldest
A-Z
Z-A
Filter by Product
Filter by Solution
28 Results
Sort & Filter
Podcast

Electronic Design: All About NoCs

Today’s SoCs are very complex. They have multiple cores and often these cores vary in type, e.g., CPUs, GPUs, and NPUs. Connecting these to peripherals and memory typically involves one or more network-on-chips (NoCs). In this podcast, Electronic Design Editor Bill Wong talks with Andy Nightingale, VP Product Management and Marketing at Arteris, about NoCs.
Podcast

SemiWiki: The Impact of Arteris on Automotive and Beyond with Frank Schirrmeister

Dan Nenni of SemiWiki is joined by Arteris’ Frank Schirrmeister in a conversation on automotive and the impact of network-on-chip IP on system design.
Podcast

SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski

SemiWiki’s Dan Nenni welcomes Michal Siwinski, CMO of Arteris, for an in-depth discussion of modern design architectures and the crucial role of Network-on-Chips (NoCs).
Podcast

EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V

The adoption of RISC-V is spreading. Versatility and “freedom to innovate” are powering the ecosystem. Frank Schirrmeister, VP Solutions and Business Development at Arteris, spoke to EE Journal’s Amelia Dalton on the fish fry podcast.
Ncore® Cache Coherent Interconnect Datasheet
Datasheet

Ncore™ Cache Coherent Interconnect IP

  • Cache coherent network-on-chip (NoC) interconnect IP
  • Arm® AMBA® CHI and ACE interoperability
  • ISO 26262-compliant functional safety mechanisms

Making Cache Coherent SoC Design Easier with Ncore
White Paper

Making Cache Coherent SoC Design Easier with Ncore™

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris makes cache coherent SoC designs easier, saving 100’s of person-years effort per project vs DIY solutions.
How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs
Webinar

How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs

Discover how our cache-coherent interconnect solution empowers multi-core SoC design teams, helping them accelerate market entry with high-quality designs and allowing more time for innovation.
Presentation

Tiled Approach to System Scaling

Today’s large-scale SoCs such as AI accelerators often deploy regular repeating arrays of processor elements. See how tiling accelerates physical design by enabling re-use of hardened physical blocks in addition to logical elements.
Previous
Next Page

No results found

Make sure all words are spelled correctly. Try different, more general, or fewer keywords.

Popup Overlay