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Podcast

EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V

The adoption of RISC-V is spreading. Versatility and “freedom to innovate” are powering the ecosystem. Frank Schirrmeister, VP Solutions and Business Development at Arteris, spoke to EE Journal’s Amelia Dalton on the fish fry podcast.
Podcast

SemiWiki: The Impact of Using a Physically Aware NoC with Charlie Janac

Arteris CEO joins SemiWiki’s Daniel Nenni on Semiconductor Insiders Podcast to discuss the impact of using a physically aware NoC.
Making Cache Coherent SoC Design Easier with Ncore
White Paper

Making Cache Coherent SoC Design Easier with Ncore™

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris makes cache coherent SoC designs easier, saving 100’s of person-years effort per project vs DIY solutions.
Presentation

Tiled Approach to System Scaling

Today’s large-scale SoCs such as AI accelerators often deploy regular repeating arrays of processor elements. See how tiling accelerates physical design by enabling re-use of hardened physical blocks in addition to logical elements.
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