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AI / Machine Learning (9) RISC-V Designs (7) Cybersecurity (6) Hardware Security Assurance (5) ISO 26262 (4) Network-on-Chip IP (4) Traceability (4) FMEDA (3) Functional Safety (3) IP-XACT (3) Magillem Connectivity (3) Multi-Die (3) Network-on-Chip (NoC) (3) FlexGen (2) FlexNoC (2) Magillem Registers (2) Power Consumption (2) Radix-S/M/ST (2) Automotive (1) CodaCache (1) Hardware/Software Interface (HSI) (1) Magillem Packaging (1) Ncore (1) Power Management (1) Routing Congestion (1) SystemC (1)
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Podcast

EE Times: When AI Meets Hardware Security

Sally Ward-Foxton speaks with Arteris’ Andreas Kuehlmann about the uGen framework’s recreation of a Spectre-v1 proof of concept, why hardware vulnerabilities are especially costly to fix after fabrication, and why AI chips may represent the next frontier in cybersecurity.
Video

Interview with Drew Barbier, VP of IP Business Unit, MIPS

Discover how MIPS and Arteris are working together to enable the next generation of physical AI. In this customer interview, Drew Barbier, Vice President of the IP Business Unit at MIPS, discusses how a software-first approach, RISC-V innovation, and close collaboration with Arteris are helping address the growing demands of AI-driven SoC design. Learn why scalable interconnect technology is essential for managing data movement, memory traffic, bandwidth, and quality of service in tomorrow's intelligent systems.
Podcast

EE Journal: Securing the Silicon: The Seismic Shift to Hardware Security

Amelia Dalton of EE Journal and Jason Oberg of Arteris explore how Cycuity’s integration into Arteris is changing the game for system-level security and discuss how teams can address the emerging risks in our era of distributed systems, chiplets, and constant data movement.
Arteris Interview with Aniket Saha, VP of Product Management, Tenstorrent
Video

Interview with Aniket Saha, VP of Product Management, Tenstorrent

Discover how Tenstorrent is using Arteris Network-on-Chip (NoC) IP to power the next generation of AI compute. In this interview, Aniket Saha, VP of Product Management, Tenstorrent, shares how Arteris silicon-proven NoC technology helped solve complex data movement challenges while providing the flexibility needed for future innovation.
Webinar: Making Automotive Semiconductor Cybersecurity Practical
Webinar

Making Automotive Semiconductor Cybersecurity Practical  

This webinar explores a practical, end-to-end approach to automotive semiconductor cybersecurity, connecting security requirements, secure IP implementation, and scalable security assurance.
Quick Reference Guides

Hardware Security Assurance Checklist

This hardware security checklist helps engineering teams evaluate the maturity of their hardware security practices across the entire development lifecycle.
White Paper

Build Secure SoCs from the Start

This eBook examines the hardware security assurance in modern semiconductor design. Discover how to detect vulnerabilities early in the development lifecycle, reduce costly silicon respins, and deliver secure silicon products with greater confidence.
Datasheet

Cycuity Radix Technology Datasheet

Is your hardware design prepared to withstand today’s complex threat landscape? Verifying the effectiveness of security functionality and protections is essential to safeguarding your designs.
Panel with Arteris, GF & Tenstorrent: RISC-V Ecosystem Growth for Physical AI
Video

Panel with Arteris, GF & Tenstorrent: RISC-V Ecosystem Growth for Physical AI

EE Times Nitin Dahad moderates a panel, "RISC-V Ecosystem growth for Physical AI" with Gabriel Yin of Arteris, Sudipto Bose of GF and Mamoru Nakano of Tenstorrent at the MIPS "Physical AI is Agentic Ai at the Edge" event in Taipei. Topics covered: Deployable, scalable robots and taking embedded intelligence to autonomy
Podcast

SemiWiki: The Growing Threat of Hardware Security Breaches and What to do About it with Dr. Andreas Kuehlmann

Daniel Nenni of SemiWiki talks with Dr. Andreas Kuehlmann of Arteris about AI-driven cyberattacks, rising hardware security threats, regulation, and how to prepare.
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