FlexGen – Arteris

Semiconductor Engineering: How Cache Coherency Simplifies AI Software

This article explains how hardware-managed cache coherency can simplify AI software by coordinating shared data across CPUs, accelerators and chiplets. The article highlights the role of coherent and non-coherent interconnects in building scalable, efficient AI SoCs, while presenting Arteris’ Ncore,

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Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects

Learn how ISO 26262 Part 11 helps semiconductor architects build safer automotive SoCs through architectural planning, automation, and functional safety.

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Embedded: Last-Level Caches Matter Even More in the HBM Era

The article explains why last-level caches (LLCs) are becoming even more important as high-bandwidth memory (HBM) is adopted for AI and high-performance computing.

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Semiconductor Engineering: Reducing Avoidable Memory Trips In HBM Systems

As AI and high-performance SoCs increasingly rely on HBM, memory bandwidth alone is no longer enough to maximize performance. This article discusses why the intelligent data movement and cache efficiency are critical to unlocking the full benefits of HBM-based architectures.

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Semiconductor Engineering: Using SystemC TLM Modeling To Solve AI Data Movement Challenges

SystemC TLM modeling helps AI chip architects analyze NoC data movement early, identify bandwidth and latency bottlenecks, optimize workload behavior, and reduce RTL-stage performance and integration risk. Learn more about how early NoC modeling improves AI system design and accelerates

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What the steam engine can teach us about modern chip design

In 1712, a quiet breakthrough …

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Semiconductor Engineering: Facilitating Complex SoC Design Through Automation And Integration

Automation and integration tools unify IP, connectivity, and software design, enabling scalable, efficient SoC development and reducing manual complexity. Learn more about how unified system definitions, automated interconnect generation, and coordinated design flows improve performance, productivity, and time-to-market in the

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Design & Reuse: Topology and Data Movement in Multi-Die Design

This article explores how multi-die design shifts the primary challenge from scaling silicon to managing data movement and system integration across chiplets. It highlights the critical role of NoC topology in controlling traffic, latency, and coherency between dies, as well

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EDN: Last-level cache has become a critical SoC design element

As AI-driven SoCs integrate increasingly heterogeneous compute engines, last-level cache (LLC) has become a critical architectural element for balancing performance, power, and determinism. Positioned between on-chip subsystems and external memory, LLC reduces latency and off-chip traffic but only when carefully

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Semiconductor Engineering: Solving Real-World AI Bottlenecks

This article explains how modern AI SoCs are increasingly limited by data movement and memory latency rather than raw compute. It highlights the role of efficient interconnects and shared last-level caches in reducing latency, power consumption, and DRAM traffic, and

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