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SemiEngineering: Memory Choices Grow

Blogs-Placeholder

Editor’s note: This is a great article by Ed Sperling at Semiconductor Engineering, so I have highlighted it here. Cache coherency in modern SoCs is discussed toward the middle of the article. -Kurt

Streamlining Interconnect Integration Accelerates Globally Distributed Design

soc platform strategy

As system on chip designs grow more complex, it becomes more and more difficult for chip companies to optimize the work of their distributed design teams. While each separate team has an area of expertise and sets their focus on a particular aspect of the SoC, the hard part comes in integrating these individual design efforts together. When something goes wrong and it doesn’t work, the company’s critical time to market advantage starts to slip.