Connected by Arteris: Navigating Integration Challenges for the RISC-V Ecosystem with Networks-on-Chips (NoCs)
Unlock RISC-V’s potential with Arteris’ NoC solutions, optimizing SoC integration, chiplet readiness, power, performance, and innovation flexibility.
Electronic Design: Advanced SoC Development Uses Next-Gen IP Integration Tools
Network-on-chip (NoC) interconnect IP and SoC integration technology enables higher product performance with lower power consumption and faster time-to-market.
Semiconductor Engineering: NoC Development – Make Or Buy?
Significant effort is involved in developing coherent NoCs from scratch.
Semiconductor Engineering: Integration Challenges For RISC-V Designs
Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
EDN: The chiplet universe is coming: What’s in it for you?
There’s a lot of talk and excitement about chiplets these days, but there’s also a lot of confusion. What is available today? What should I expect in terms of interoperability?
Connected by Arteris: Watching The Next Big Semiconductor Transition Unfold
Explore the insights from the Chiplet Summit with Frank Schirrmeister. Discover the latest in semiconductor design, chiplet innovations, and the future of the industry.
SemiWiki: Moderating Our Open Chiplet Enthusiasm. A NoC Perspective
Insightful chiplet article from SemiWiki blogger Bernard Murphy in conversation with Arteris’ Frank Schirrmeister. Network-on-chip IP enables efficient communication among disparate chiplets.
Electronic Design: Navigating the Hardware-Software Interface in Chip Design
The hardware-software interface (HSI) is critical in chip design, bridging the physical hardware and its software counterpart, providing integration and performance optimization.
EETimes: Charlie Janac: Pick a Viable Path, Don’t Give Up
Arteris CEO Charlie Janac gives EE Times a glimpse of his 40 years in the EE industry in this engaging conversation with Nitin Dahad for Silicon Grapevine.
EDN: SoC design: When a network-on-chip meets cache coherency
Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.