Design & Reuse: Streamlining SoC Integration With the Power of Automation
The rapid acceleration of semiconductor technologies is creating system-on-chip (SoC) devices that are increasingly complex.
SemiWiki: Pairing RISC-V Cores With NoCs Ties SoC Protocols Together
Designers have many paths for differentiating RISC-V solutions.
Semiconductor Engineering: NoC Experiences From The Trenches
Network-on-chip (NoC) interconnect as an alternative to traditional crossbars is already well-proven, but there are still plenty of design teams on the cusp of a transition
EDN: Accelerating RISC-V development with network-on-chip IP
In the world of system-on-chip (SoC) devices, architects encounter many options when configuring the processor subsystem.
Semiconductor Engineering: Network-On-Chips Enabling Artificial Intelligence/Machine Learning Everywhere
What goes on between the sensor and the data center.
EE Times: Handling the Challenges of Building HPC Systems We Need
What is the secret of humanity’s success? What has given us the ability to build wonders, such as Stonehenge in England
Electronic Design: Optimize SoC Design with a Network-on-Chip Strategy
Today’s system-on-chip (SoC) devices can contain hundreds of millions to over a hundred billion transistors
Semiconductor Engineering: Design Complexity In The Golden Age Of Semiconductors
While writing last month’s blog that used some of the trend charts we have seen, I noticed that a lot of the data ends in 2020
SemiWiki: #60DAC Update from Arteris
I met up with Andy Nightingale, VP Product Marketing and Michal Siwinski, Chief Marketing Officer of Arteris at #60DAC for an update on their system IP company dealing
EDN: Network-on-chip (NoC) interconnect topologies explained
Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks