Semiconductor Engineering: DAC 2023: Megatrends And The Road Ahead For Design Automation
As Silicon Valley is in the midst of the heat wave the world is experiencing, the recent Design Automation Conference and its exhibition discussed hot technologies.
Semiconductor Engineering: The Design Automation Conference Turns 60! What’s Hot? What’s Next?
This coming week from July 9th to July 13th, experts from all over the world will descend on the Moscone Center in San Francisco
SemiWiki: Back to Basics – Designing Out PPA Risk
I wrote earlier about managing service-level risk in SoC design, since the minimum service level a system can guarantee under realistic traffic is critical to OEM guarantees
Semiconductor Engineering: Megatrends At DAC
Spotting key trends over three days of a semiconductor design conference is a challenge, but some important ones come into focus after attending multiple sessions — AI/ML, chiplet
Design & Reuse: Push-Button NoCs for SoCs
Today’s system-on-chip (SoC) devices may be composed of hundreds of functional blocks known as intellectual property (IP) blocks. Each of these IPs can contain hundreds of millions of transistors.
EDN: SoC Design: When is a network-on-chip not enough?
In the not-so-distant past, system-on-chip (SoC) devices were relatively simple compared to today’s offerings. Early SoCs typically consisted of 10 to 20 intellectual property (IP) blocks, each generally
Semiconductor Engineering: How Many Senses Do You Need To Drive A Car?
The recent AutoSens conference in Detroit left me questioning whether I should turn in my driver’s license. The answer the attending OEMs gave to all the discussions about the advantages
SemiWiki: Managing Service Level Risk in SoC Design
Discussion on design metrics tends to revolve around power, performance, safety, and security. All of these are important, but there is an additional performance objective a product must meet defined by a minimum
EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
Physically aware network-on-chips take center stage in this week’s Fish Fry podcast! Andy Nightingale from Arteris and I investigate the role that network-on-chips have played in the development of SoC designs.
SemiWiki: Is Your Interconnect Strategy Scalable?
“Strategy” is a word sometimes used loosely to lend an aura of visionary thinking, but in this context, it has a very concrete meaning. Without a strategy, you may be stuck with decisions