Semiconductor Engineering: How Safe Is Safe Enough?
That was the overarching question a group of 180 experts discussed last week at the ISO 26262 & SOTIF conference for four days during #FuSaWeek2023 in Berlin. “How Safe is Safe
EETimes: How to Avoid Fall in Expectations for Automated Driving
Consider that there were more than 38,824 automotive fatalities and 115,000 injury accidents in 2020 in the United States alone, according to the U.S. Department of Transportation.
SemiWiki: Interconnect Under the Spotlight as Core Counts Accelerate
In the march to more capable, faster, smaller, and lower power systems, Moore’s Law gave software a free ride for over 30 years or so purely on semiconductor process evolution. Compute hardware
EDN: Create high-performance SoCs using network-on-chip IP
A system-on-chip (SoC) containing a million transistors was considered a large device in the not-so-distant past. Today, SoCs commonly contain up to a billion transistors. Consider, for example
Semiconductor Engineering: Physically Aware NoCs
More functions, greater security risks, and increasingly complicated integration of IP and various components below 7nm is increasing the time and effort it takes to get a functioning chip
Electronic Design Article: Physically Aware Network-on-Chip Streamlines SoC Design Cycle
Arteris IP has released FlexNoC 5, a network-on-chip (NoC) IP configuration tool, designed to improve system-on-chip (SoC) designs and streamline the design cycle. I spoke with Arteris IP’s VP
EDN Article: How physically aware interconnect IP bolsters SoC design
The network-on-chip (NoC) technology, which connects IP blocks in highly complex system-on-chip (SoC) designs, has ascended to the next logical level by becoming physically aware.
Semiconductor Engineering: The Game Of Ecosystems Intensifies
You may know about my fascination with ecosystems if you have followed my writing. It is only fitting that I am writing this Blog in Munich (shiver, it’s cold), where I attended the GSA
Design News: Network On-Chip IP Speeds SoC Development
Spencer Chin, Senior Editor for Design News, authored this Design News Article on Arteris’ FlexNoC 5.
EE Journal: I hear you NOCing, But Can You Close Timing?
Network on Chip (NOC) IP has been around for a while. I wrote an article about academic research papers on NOCs presented at the seventh annual International Symposium on System-on-Chip