Semiconductor Engineering: Edge Complexity To Grow For 5G

Kurt Shuler, VP of Marketing at Arteris IP, said, You may have to reboot part of the chip for a failed operation while keeping the rest in a safe state.
EE Times article, SoC Interconnect: Don’t DIY!

Kurt Shuler, VP Marketing at Arteris IP, explains why a DIY approach to building your own configurable interconnect IP product is not as easy as one may think.
SemiWiki: Intelligence in the Fog

Kurt Shuler, VP Marketing at Arteris IP, and Bernard Murphy (SemiWiki) discuss the hottest domains in tech today – AI and automotive in this new SemiWiki blog.
Semiconductor Engineering: Machine Learning Drives High-Level Synthesis Boom

Kurt Shuler, VP of Marketing at Arteris IP, said, The software architect calling the shots, chip was defined by the algorithm, not the other way around.
SemiWiki: What are SOTIF and Fail-Operational and Does This Affect You?

Kurt Shuler, VP Marketing at Arteris IP, and Bernard Murphy (SemiWiki) discuss Safety of the Intended Function (SOTIF) in this latest SemiWiki blog.
Semiconductor Engineering: Chiplet Momentum Builds, Despite Tradeoffs

Arteris IP’s Kurt Shuler, Vice President of Marketing, contributes to this latest article in Semiconductor Engineering.
Semiconductor Engineering: Make Your Own Energy

Arteris IP’s Kurt Shuler, Vice President of Marketing, quoted in the latest Semiconductor Engineering article.
Semiconductor Engineering: Interconnect Prominence In Fail-Operational Architectures

Arteris’ Kurt Shuler, Vice President of Marketing, authored this latest article in Semiconductor Engineering about moving toward “Fail Operational”
SemiWiki: ML and Memories: A Complex Relationship

Kurt Shuler, VP Marketing at Arteris IP, helped Bernard Murphy (SemiWiki) learn the multiple ways that different types of memory need to connect to these accelerators in the latest SemiWiki blog.
Semiconductor Engineering: The Long and Detailed Road to Automotive Compliance

Arteris’ Kurt Shuler, Vice President of Marketing, comments in the latest Semiconductor Engineering article.