Silicon Semiconductor: Revolutionizing Semiconductor Design
Phil Alsop, Editor of Silicon Semiconductor Magazine, discusses exciting developments with Arteris’ Andy Nightingale including the launch of FlexGen and the immediate availability of the latest generation of Magillem Registers technology for SoC integration automation.
EE Times: SoCs Get a Helping Hand from AI Platform FlexGen
Explore how AI-driven tools are transforming chip design, tackling the growing complexity in industries like AI, autonomous driving, and cloud computing. Learn how solutions such as FlexGen boost productivity, streamline iterations, and optimize power and performance for cutting-edge technologies.
Semiconductor Engineering: Optimizing Data Movement In SoCs And Advanced Packages
Explore how the growing demand for low-latency on-chip communication and the need for managing all of this with less power and using a simpler setup can be met.
SemiWiki: How Arteris FlexGen Smart NoC IP Democratizes Advanced Chip Design
SemiWiki’s Dan Nenni explores the capabilities and impact of Arteris FlexGen – Smart NoC IP with Rick Bye, director of Product Management and Marketing at Arteris. This revolutionary product uses cutting-edge AI heuristics and machine learning to automate NoC generation and deliver expert-level results without the expert or length design cycles
Design News: How Can Network On-Chip IP Can Meet System-On-Chip Demands?
Arteris recently developed FlexGen IP for system-on-chip design. In this conversation with Design News, Rick Bye, Arteris’s Director of Product Management and Marketing, talks about the product’s function and applications.
Semiconductor Engineering: Verification Experts Vs. Generalists
The increasing complexity of design is driving specialization and innovative approaches in verification — and some interesting arguments. Read the full discussion of the expert panel here.
EDN: How AI is changing the game for high-performance SoC designs
The rapid increase in SoC complexity has exceeded the capabilities of traditional NoC design methodologies. Learn more about the smart NoC IP alternatives in this article.
RISC-V: Soft Tiling RISC-V Processor Clusters Speed Design and Reduce Risk
Discover how Arteris’ NoC soft tiling tech accelerates RISC-V processor cluster design, boosting scalability and reducing errors in complex SoCs.
Semiconductor Engineering: Top 5 Reasons Engineers Need A Smart NoC
As system-on-chip (SoC) designs grow more complex, IP interconnect engineers struggle with achieving optimal scalability, performance, and power efficiency. Learn how Arteris’ FlexGen smart NoC IP could help deliver future-ready SoCs.
SemiWiki: Is Arteris Poised to Enable Next Generation System Design?
The semiconductor industry is transitioning to multi-die designs driven by AI. Arteris is leading the way by tackling challenges like the ‘memory wall’ using cache-coherent NoC and Magillem technology for efficient IP management. Learn more in the article.