SemiWiki’s Dan Nenni welcomes Michal Siwinski, CMO of Arteris, for an in-depth discussion of modern design architectures and the crucial role of Network-on-Chips (NoCs).

Discover how NoC architectures overcome the limitations of bus structures, optimize data flow, and ensure consistent memory access in complex SoCs.

There are a myriad of approaches, and each serves a unique purpose in optimizing performance and efficiency.

Arteris Magillem conquers challenges of AI, multi-die, & CI design with structured assembly. Discover why top chipmakers are crossing the chasm & ditching DIY tools. Learn more about connectivity, register management, & HW/SW co-design.

Top experts reveal challenges & opportunities! Learn about multi-vendor vs. single-vendor designs, automotive concerns, interoperability woes, and the path to off-the-shelf chiplet nirvana. Deep insights from RISC-V Summit panel (Arteris, Tenstorrent, Ventana Micro, Synopsys). Explore the future of high-performance, modular

Trends shaping chip design and what might be ahead in the next year.

RISC-V tends to generate excitement over the possibilities for the processor core, any custom instruction extensions, and its attached memory subsystem.

The majority of today’s ICs employ some form of NoC, but how will the NoC-based chiplets communicate with each other?

The adoption of RISC-V is spreading. Versatility and “freedom to innovate” are powering the ecosystem.

Control and status register mismanagement can lead to expensive oversights.