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FlexNoC Interconnect IP

Physically aware network-on-chip IP designed to speed development.

FlexNoC Interconnect IP

Overview

Enabling SoC developers to create physically valid NoCs faster

FlexNoC® Interconnect IP is used by the world’s top semiconductor design teams as the backbone for on-chip communications in chips that target the fastest growing markets. It enables efficient data movement and provides flexibility in complex designs. FlexNoC benefits include:

Accelerate development cycles
Increase system performance
Reduce latency
Improve quality of results
Increase power efficiency

Using both FlexNoC and Ncore IP in an ASIC design also delivers unparalleled performance optimization, scalability, and system integration. This in turn supports market differentiation and helps accelerate time to market.

Advantages

A comprehensive NoC IP product for creating
the world’s best SoCs

Flexible topologies

FlexNoC is generated from simple elementary components, combined using a powerful set of underlying algorithms and an intuitive GUI, making it possible to build any topology.

Small to large SoCs

FlexNoC easily supports long cross-chip paths by leveraging source-synchronous communications and virtual channels.

Huge bandwidth

FlexNoC drives performant on-chip data flow and access to off-chip memory by enabling multichannel HBMx memory and high-bandwidth data paths.

FlexNoC 5 key features

Auto-timing closure assist
NIU (Network Interface Unit) tiling to organize NIUs into modular, repeatable blocks, improving scalability, efficiency, and reliability
Topology visualized directly on floorplan
Multi-clock/power/voltage domains and power management with unit-level clock gating
Multi-protocol support including AMBA 5 with QoS bandwidth regulator and limiter enumerations
General optimizations for lower area e.g. up to 30% for some NoC elements depending on configuration
Native and user-defined firewall security
Import and export to Magillem tools
AMBA 5 support of DVM 8.1 (Distributed Virtual Memory)
On-chip performance monitoring and debug
Debug and trace with ATB 128b and timestamps

Show More Features

Explore additional FlexNoC features, download the datasheet.

Efficient data movement through the SoC

Integration with Arteris CodaCache® last-level cache raises the bar on innovation:

Ideal for NoC applications with data re-use
Improves overall SoC latency and power

Efficient data movement through the SoC

NoC integration automated flow

Automated flow to leverage SoC connectivity information using Arteris Magillem:

Improved productivity with reduced process
Better quality with early error detections thanks to checkers

NoC integration automated flow

FlexNoC product benefits

Higher frequencies, lower latencies

Use built-in NoC performance analysis exploration tools.

Reduced power consumption

Advanced power management through clock gating, DVFS, and GALS.

Smaller die area

Fewer wires using optimal NoC transport layer.

Speedy timing closure

Early physical awareness for faster convergence without redesigns.

Easy configuration

Use the intuitive FlexNoC UI.

Automated verification

Save hundreds of hours of work compared to manual verification test benches.

Shorter schedules

Speed time to market with fewer iteration loops.

Higher profit

Reduce time to market with FlexNoC design efficiency savings.

Product comparison table

Category	Features	FlexNoC	FlexGen	FlexGen Multi-Die
Target Audience and Scale	Smaller-scale MCU SoCs
	Small-medium scale SoCs
	Large scale SoCs
	Multi-Die SoCs
Instances per Design	Single NoC instance
Instances per Design	Multiple NoC instances
Network Interface Units (NIUs)	Up to 50 NIUs
	Up to 200 NIUs
	Up to 1000 NIUs	XL option	XL option	XL option
	Up to 2000 NIUs		2XL option	2XL option
Compatibility	AXI, AHB, APB, OCP, PIF, AMBA 5
Compatibility	ACE-Lite
Smart NoC Automation	Topology generation with minimum wire length
	Scripting driven regular topology creation
	Incremental design capability
	Wire congestion statistics reporting option		Included
Physical Awareness	Automatic timing closure assistance
Physical Awareness	Floorplan visualization
Chiplet-to-Chiplet NoC connectivity	PHY agnostic FlexGen Die-to-Die IP
Chiplet-to-Chiplet NoC connectivity	Adapator layer for third-party PHY			Coming soon
Advanced Scalability	Enhanced Tiling (partial network)^1,2	XL option	XL/2XL options	XL/2XL options
	Mesh topology editor	XL option	XL/2XL options	XL/2XL options
	Write broadcast stations	XL option	XL/2XL options	XL/2XL options
	Virtual channel links	XL option	XL/2XL options	XL/2XL options
	Source synchronous asynchronous bridges	XL option	XL/2XL options	XL/2XL options
	Up to 1024 bits data bus	XL option	XL option	XL option
	Up to 2048 bits data bus		2XL option	2XL option
	512 pending transaction support	XL option	XL option	XL option
	1024 pending transaction support		2XL option	2XL option
Optimizations	Optimization for performance, area, and wire length
	Advanced quality of service (QoS)
	Power management and security
	Address and data protection schemes
	Advanced in-circuit debug features
	Multi-cycle SRAM support
Add-On Options	Memory Reorder Buffer Option
	Reliability Option
	Safety (up to ISO 26262 ASIL-D) Option
	Advanced Scalability Options (XL and 2XL)

¹ NIU limits apply per individual monolithic die or chiplet design.

² FlexGen is advised for customers seeking to create a mesh topology using tiling.

³ Customers seeking to license multiple optional features should disclose its requirements to Arteris support engineers. Given the increasing complexity of designs, customers are advised to communicate their specific design needs to Arteris support engineers.

FlexNoC fully integrated product options

Option

Large Systems: XL and 2XL

Enhanced tiling
Mesh topology editor
Up to 2048 bits data bus
Virtual channel links
Write broadcast stations

Learn more about product

Option

Resilience: Safety

ISO 26262 Functional Safety (FuSa)
Multi-ASIL support
Interconnect-wide ECC support

Learn more about product

Option

Performance: Reorder Buffer

Single and multichannel reorder buffers (ROB):

Avoid ordering rule blocks
Avoid response serialization bottlenecks
Allow concurrent memory channel reads

Learn more about product

Featured Solution

面向芯粒时代的 Multi-Die 解决方案

随着 AI 系统突破单芯片（Single-Die）架构限制，迈向 Multi-Die 多芯粒架构时代，Arteris 在支持硅系统持续扩展的同时，始终保持一致的系统架构。

将智能 NoC 数据传输能力扩展至裸片（Die）边界之外
保留 QoS、虚拟通道以及原始设计意图
通过自动化技术与安全机制简化芯片集成

Arteris Multi-Die 解决方案帮助工程团队在多个裸片之间进行系统划分与部署，同时保持统一的架构设计，从而缩短开发周期并降低系统集成风险。

Customer Testimonials

Trusted by innovative
 companies everywhere

Sondrel has deployed Arteris FlexNoC interconnect IP across several customer SoC projects to great effect. Physical constraints have always been an important issue and are even more important below 16nm geometries. The latest FlexNoC 5 with its physical awareness technology, enables our RTL teams to verify that architectures meet physical constraints and provide a better starting point for our place and route team. We look forward to our continued cooperation with Arteris.

Using Arteris FlexNoC allows us to reduce development time and manage project risk. FlexNoC’s advanced quality-of-service and debugging features, combined with its multi-protocol support, allow Samsung SUHD TVs to reduce power consumption and die area for complex chips with more than 100 IP interfaces.

FlexNoC interconnect IP allowed us to dramatically increase MCU performance and functionality with no impact on die area while significantly decreasing power consumption.

As a result of our thorough evaluation, we know the Arteris FlexNoC interconnect IP will help us shorten development schedules and increase product performance, while simultaneously decreasing costs due to back-end wire routing congestion and timing closure issues.

By incorporating Arteris FlexNoC interconnect IP into our development programs, we are able to streamline our overall design time. This solution also provides us with flexibility to create derivations of our offerings to quickly adapt to changing market needs.

TSMC chose to work with Arteris on the interposer based test chip program because its interconnect technology is ideally suited to addressing the SoC wire routing congestion and timing closure challenges. TSMC and Arteris are working together to make it easier for our joint customers to adopt these technologies.

Our successful adoption of Arteris FlexNoC fabric IP has been straightforward, allowing us to more quickly architect and implement sophisticated systems-on-chip in less time and with better power consumption and performance.

Resources

Datasheet

FlexNoC® 5 Interconnect IP Datasheet

Non-coherent network-on-chip (NoC) interconnect IP
Protocol interoperability: AMBA 5, ACE-Lite, AXI, AHB, APB; OCP; PIF
Reduce wire routing congestion, die area & power consumption

Case Studies

Datasheets

Infographics

Accelerating Timing Closure for Networks-on-Chip (NoCs) With Physical Awareness

Podcasts

Presentations

Solution Briefs

Accelerate, Optimize, and Secure AI-Based SoC Designs with Arteris

Videos

Webinars

White Papers

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