Products

Arteris provides semiconductor technology that optimizes data movement, accelerates SoC integration, and enables secure, high-performance, power-efficient silicon. Arteris technology has shipped in more than 4+ billion chips and chiplets across AI, automotive, enterprise computing, consumer electronics, industrial, and other markets.

Coherent Interconnect

Arteris coherent interconnect technology is critical for complex multi-core and heterogeneous systems, efficiently connecting multiple processing elements inside an SoC or across chiplets.

Coherent Interconnect

Ncore Cache Coherent Interconnect IP

Ncore IP simplifies multi-core SoC design with heterogeneous coherency, efficient caching, and high throughput, for reliable, high-performance with ISO 26262 support.

Non-Coherent Interconnect

Essential for efficient NoC designs, highly configurable Arteris network-on-chip fabric technology brings physical awareness to help accelerate timing closure, reduce wires, and increase SoC performance.

Non-Coherent Interconnect IP

FlexGen Smart Interconnect IP

Smart NoC IP automates the creation of high-performance NoC designs for a 10x productivity boost and up to a 30% wirelength reduction, reducing latency and power consumption.

Non-Coherent Interconnect IP

FlexNoC Interconnect IP

Physically aware NoC IP with an ISO 26262 support option, delivering up to 5x reduced turnaround times on timing closure versus manual physical iterations.

Non-Coherent Interconnect IP

FlexWay Interconnect IP

FlexWay is particularly well-suited to cost-efficient, low-power IoT edge devices and microcontrollers (MCUs), and comes available with ISO 26262 support.

Category	Features	FlexNoC	FlexGen	FlexGen Multi-Die
Target Audience and Scale	Smaller-scale MCU SoCs
	Small-medium scale SoCs
	Large scale SoCs
	Multi-Die SoCs
Instances per Design	Single NoC instance
Instances per Design	Multiple NoC instances
Network Interface Units (NIUs)	Up to 50 NIUs
	Up to 200 NIUs
	Up to 1000 NIUs	XL option	XL option	XL option
	Up to 2000 NIUs		2XL option	2XL option
Compatibility	AXI, AHB, APB, OCP, PIF, AMBA 5
Compatibility	ACE-Lite
Smart NoC Automation	Topology generation with minimum wire length
	Scripting driven regular topology creation
	Incremental design capability
	Wire congestion statistics reporting option		Included
Physical Awareness	Automatic timing closure assistance
Physical Awareness	Floorplan visualization
Chiplet-to-Chiplet NoC connectivity	PHY agnostic FlexGen Die-to-Die IP
Chiplet-to-Chiplet NoC connectivity	Adapator layer for third-party PHY			Coming soon
Advanced Scalability	Enhanced Tiling (partial network)^1,2	XL option	XL/2XL options	XL/2XL options
	Mesh topology editor	XL option	XL/2XL options	XL/2XL options
	Write broadcast stations	XL option	XL/2XL options	XL/2XL options
	Virtual channel links	XL option	XL/2XL options	XL/2XL options
	Source synchronous asynchronous bridges	XL option	XL/2XL options	XL/2XL options
	Up to 1024 bits data bus	XL option	XL option	XL option
	Up to 2048 bits data bus		2XL option	2XL option
	512 pending transaction support	XL option	XL option	XL option
	1024 pending transaction support		2XL option	2XL option
Optimizations	Optimization for performance, area, and wire length
	Advanced quality of service (QoS)
	Power management and security
	Address and data protection schemes
	Advanced in-circuit debug features
	Multi-cycle SRAM support
Add-On Options	Memory Reorder Buffer Option
	Reliability Option
	Safety (up to ISO 26262 ASIL-D) Option
	Advanced Scalability Options (XL and 2XL)

¹ NIU limits apply per individual monolithic die or chiplet design.

² FlexGen is advised for customers seeking to create a mesh topology using tiling.

³ Customers seeking to license multiple optional features should disclose its requirements to Arteris support engineers. Given the increasing complexity of designs, customers are advised to communicate their specific design needs to Arteris support engineers.

Last-Level Cache

Arteris helps ensure the last-level cache (LLC) performs optimally with interconnect IP that efficiently moves high-bandwidth data in and out of the cache, preserves predictable latency, and supports flexible partitioning for varying workloads.

Last-Level Cache

CodaCache Last-Level Cache IP

A highly configurable caching solution to optimize SoC performance and address key SoC challenges, such as power efficiency, data access, timing closure, and layout congestion.

SoC Connectivity

Arteris simplifies IP packaging and SoC assembly with the efficient management of all aspects of system integration. This helps make the design process easier, faster, and less risky, increasing productivity and freeing teams to focus on product differentiation.

SoC Connectivity

Magillem Connectivity

Automation tools and built-in checkers to boost productivity, accelerate TTM and improve design quality, while shortening, streamlining, and de-risking the integration process.

SoC Connectivity

Magillem Packaging

A fully automated solution to import legacy RTL and create a correct by-construction IP-XACT description, map the physical ports into the bus interface, and capture the memory map.

Category	Features	Magillem Packaging	Magillem Connectivity	Magillem Registers
IP-XACT Conversion	2009 to 2022
IP-XACT Conversion	2014 to 2022
Resource Management	Projects
	Catalogs
	Components
TGI	TGI API
HDL Import	Verilog/SystemVerilog support
HDL Import	View & FileSet elaboration
Bus Interface	Auto mapping
Rules Checkers	Design and component
	Memory and system map
	Configurable checker severity
Assembly	Rule-based connectivity
	Bus/signal split/tie/open/feedthrough
	Glue logic insertion
RTL Netlist Generation	Configurable header
	Keep parameter expressions
	Signals/netname/tie management
Hierarchical Manipulations	Merge, Flatten, Move operations
Hierarchical Manipulations	Parameter propagation
IP Update	Rename/resize/delete/merge
IP Update	User mapping rules definition
Diff and Merge	Accept/Reject any change
Diff and Merge	Conflict resolution wizard
Import Memory Map Description	SystemRDL support
	IP-XACT support
	Excel spreadsheets support
Generate HSI Outputs	RTL register bank (VHDL, Verilog, SystemVerilog)
	Customized C Header files
	UVM RAL files
	Documentation (Word, FrameMaker, HTML)
	SystemRDL description
	IP-XACT description

Hardware/Software Interface

Arteris provides a single source of truth environment for the effective collaborative development of the software and hardware interface, keeping all design teams in sync while mitigating design errors.

Hardware / Software Interface

Magillem Registers

Importing the memory map description in Magillem Registers helps ensure synchronization between hardware, software, and documentation for automatic, consistent data generation.