Enterprise SSD endurance and data reliability require unique interconnect features in host controller SoCs.

Winners, losers and observations from the Consumer Electronics Show

Like a helicopter grinding itself to death, flash memory requires preventative maintenance to meet enterprise SSD UBER and MTTF reliability requirements.

Editor’s note: This is a great article by Ed Sperling at Semiconductor Engineering, so I have highlighted it here. Cache coherency in modern SoCs is discussed toward the middle of the article. -Kurt

Greater productivity, lower power, smaller die size and greater bandwidth await teams that adopt proven methodologies to streamline design in mature geometries.

It’s incumbent on IP vendors to deliver higher quality designs that enable a smoother back-end process.

As system on chip designs grow more complex, it becomes more and more difficult for chip companies to optimize the work of their distributed design teams. While each separate team has an area of expertise and sets their focus on

Author’s note: This article was originally published in Design & Reuse where it has been read by nearly 2,000 engineers and shared by over 100 people.

A glossary of ISO 26262 abbreviations and acronyms can be a great help to understanding functional safety standards.

The rules are changing for the semi industry and vendors had better find ways to be more competitive or they will find themselves designed out.