IP Transaction Protocols: Plug and Play AMBA, OCP and others
As engineers, we view transaction protocols as simply a language to be able to communicate information from one block of system-on-chip (SoC) IP to another block. However, if you look at transaction protocols from an economics framework you see there’s much more to it. With the past interconnect fabrics dominated by crossbars and hierarchal busses, the choice of the IP transaction protocol created a humongous switching cost.
Hogan NoC analysis – Sonics SGN, Arteris FlexNoC, ARM NIC 400: Setting the record straight
Recently, Sonics board member Jim Hogan uploaded some content onto deepchip.com (http://www.deepchip.com/items/0511-06.html) that purports to provide unbiased guidance regarding metrics for evaluating network-on-chip technology and interconnect fabrics. I applaud Jim for his analysis of the metrics one should use to evaluate SoC interconnects.
SMP, Asymmetric Multiprocessing, and the HSA Foundation
When we hear the term “multiprocessing,” we often associate it with “symmetric multiprocessing (SMP).” This is because of SMP’s initial prevalence in the high-performance computing world, and now in x86/x64 servers and PCs. However, it’s been known for years that SMP’s ability to scale performance as the number of cores increases is poor.
The Gartner Hype Cycle & Technology Adoption Lifecycle Explained (using NoC Technology)
My purpose in this article is to explain Gartner Research’s Hype Cycle and relate it to the Technology Adoption Lifecycle popularized by Geoffrey Moore’s book, “Crossing the Chasm
Updated Interface Standards Table – MIPI HSI, HSIC, UniPro, UniPort, LLI, C2C
I’ve received a lot of feedback on the “Interchip Connectivity: HSIC, UniPro, HSI, C2C, LLI…oh my!” article I wrote last year and I thank everyone for their feedback!
Interchip Connectivity: C2C, MIPI LLI and the path to 3D IC and TSV
It may seem strange to link two interchip interface standards to the future of 3D integrated circuits, but please bear with me for a few minutes. I hope to prove that the learning from today will impact how we design SoCs in the near future.
Semiconductor Slowdown? Invest!
Samsung’s announcement that it is investing a company-record $42B in 2012 for technology development came as a bit of a shock to many in the financial and technology press. The size of this investment dwarfs that of any other company I know of, and even exceeds the expected technology investments of entire nations, such as the combined investments of the Japanese semiconductor vendors.
MIPI LLI or C2C?
Two new options for interchip connectivity are available today that enable sharing a DRAM memory between two chips for data and programs. These standards, called MIPI Low Latency Interface (MIPI LLI) and Chip-to-Chip (C2C), are primarily targeted at mobile phones, where a mobile phone’s modem usually requires its own discreet DRAM. With either C2C or MIPI LLI, the mobile phone modem can use the application processor’s DRAM though a low-latency, memory-mapped connection that requires no software drivers or runtime software.
NoC Interconnect Technology Becoming Mainstream
Gartner analyst Jim Tully’s assessment that network on chip (NoC) technology will be “mainstream” in two to five years is an acknowledgement of the technical and commercial success NoC interconnect IP has had in the consumer electronics system on chip (SoC) market over the last couple of years.
How to Calculate Late Time to Market (TTM) Revenue Loss, Part 1
When I speak to semiconductor product managers, directors and VPs, one of the questions I often ask is, “How much does it cost you if your chip is one month late?”