As engineers, we view transaction protocols as simply a language to be able to communicate information from one block of system-on-chip (SoC) IP to another block. However, if you look at transaction protocols from an economics framework you see there’s

Recently, Sonics board member Jim Hogan uploaded some content onto deepchip.com (http://www.deepchip.com/items/0511-06.html) that purports to provide unbiased guidance regarding metrics for evaluating network-on-chip technology and interconnect fabrics. I applaud Jim for his analysis of the metrics one should use to

When we hear the term “multiprocessing,” we often associate it with “symmetric multiprocessing (SMP).” This is because of SMP’s initial prevalence in the high-performance computing world, and now in x86/x64 servers and PCs. However, it’s been known for years that

My purpose in this article is to explain Gartner Research’s Hype Cycle and relate it to the Technology Adoption Lifecycle popularized by Geoffrey Moore’s book, “Crossing the Chasm

I’ve received a lot of feedback on the “Interchip Connectivity: HSIC, UniPro, HSI, C2C, LLI…oh my!” article I wrote last year and I thank everyone for their feedback!

It may seem strange to link two interchip interface standards to the future of 3D integrated circuits, but please bear with me for a few minutes. I hope to prove that the learning from today will impact how we design

Samsung’s announcement that it is investing a company-record $42B in 2012 for technology development came as a bit of a shock to many in the financial and technology press. The size of this investment dwarfs that of any other company

Two new options for interchip connectivity are available today that enable sharing a DRAM memory between two chips for data and programs. These standards, called MIPI Low Latency Interface (MIPI LLI) and Chip-to-Chip (C2C), are primarily targeted at mobile phones,

Gartner analyst Jim Tully’s assessment that network on chip (NoC) technology will be “mainstream” in two to five years is an acknowledgement of the technical and commercial success NoC interconnect IP has had in the consumer electronics system on chip

When I speak to semiconductor product managers, directors and VPs, one of the questions I often ask is, “How much does it cost you if your chip is one month late?”