Managing SoC integration is complex. Integrating content from various sources often results in problems deep in the product development cycle. Get it right the first time with automation.

Arteris and Arm announced an update to their partnership. This prompts the question: where are coherent and non-coherent NoCs in automotive systems? Let’s find out.

Why maintaining flexibility in coherency is essential in heterogeneous designs. A video discussion with Semiconductor Engineering’s Ed Sperling.

Designing a NoC is hard enough on a good day. It’s significantly more difficult to develop a coherent NoC. This is why design teams need to use NoC IP.

Dan Nenni of SemiWiki is joined by Arteris’ Frank Schirrmeister in a conversation on automotive and the impact of network-on-chip IP on system design.

The advantages of cache go beyond processor clusters and are equally applicable to many other complex IPs including AI accelerators.

In the same way that Arm leads in providing the processor portion of automotive SoCs, Arteris is the NoC interconnect leader. Together, it’s a powerful solution.

There is a dramatic difference between processor and memory performance. Ncore can reduce the overhead for implementing cache coherent architectures, breaking down the memory wall.