Network-on-chip (NoC) interconnect IP and SoC integration technology enables higher product performance with lower power consumption and faster time-to-market.

Significant effort is involved in developing coherent NoCs from scratch.

Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.

There’s a lot of talk and excitement about chiplets these days, but there’s also a lot of confusion. What is available today? What should I expect in terms of interoperability?

Insightful chiplet article from SemiWiki blogger Bernard Murphy in conversation with Arteris’ Frank Schirrmeister. Network-on-chip IP enables efficient communication among disparate chiplets.

The hardware-software interface (HSI) is critical in chip design, bridging the physical hardware and its software counterpart, providing integration and performance optimization.

Arteris CEO Charlie Janac gives EE Times a glimpse of his 40 years in the EE industry in this engaging conversation with Nitin Dahad for Silicon Grapevine.

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of