An emphasis on physical awareness significantly reduces the iterative cycles of NoC placement and routing.

Integrating cache memory into SoCs and IP blocks improves their performance and efficiency. This article highlights technologies and strategies to address challenges like cache coherency and power consumption.

Learn about sidestepping data incompatibility issues in heterogeneous chip designs.

SoC design complexity is exploding. CSRCompiler automates hardware/software interface (HSI) tasks, reduces errors, and cuts the HSI development process by up to one-third, minimizing frustration, increasing productivity, reducing risk, and speeding time to market.

Arteris brings cutting-edge technology to DAC 2024, empowering engineers to create high-performance SoCs with greater efficiency.

Creating a new implementation of an SoC from the ground up is resource-intensive, time-consuming, and expensive. Learn how NoC IP from Arteris was used to bring a derivative design to market faster.

SemiWiki’s Mike Gianfagna chatted with Arteris’ Insaf Meliane about the challenges of SoC integration and how Arteris is helping companies reduce design time while improving the quality of the design.

Many SoC developers enjoy the challenge of squeezing the highest performance possible out of their designs. Is deploying last-level cache the answer?

Managing FuSa-enhanced CSRs is a challenge. New solutions enable quick, scalable automation reducing the time to generate the HSI for SoCs.

Modern SoCs require proven network-on-chip (NoC) IP. Commercial NoCs, coherent or non-coherent, offer tremendous advantages to design teams and the end product.