Overview
面向下一代 SoC 设计的智能片上网络（NoC）自动化
Arteris FlexGen® Multi-Die 在 Arteris FlexGen 智能 NoC IP 的基础上新增裸片间（Die-to-Die）控制器 IP，实现芯粒与芯粒之间的互连。该解决方案利用先进的 AI 启发式算法和机器学习技术，可自动生成单芯片（Monolithic）及 Multi-die 设计的 NoC 拓扑结构，相较于传统手动 NoC 设计方法，设计迭代速度最高可提升 10 倍。
- 优化布线长度
- 降低系统延迟
- 提升功耗效率
- 高效连接跨芯粒的 FlexGen NoC
- 最大程度减少人工干预
专为高性能计算（HPC）和 AI 加速器应用打造，广泛适用于数据中心、汽车电子、消费电子及工业电子领域。FlexGen Multi-Die 能够显著缩短设计周期，帮助客户加速产品上市时间，并支持对复杂系统架构进行更多设计方案探索与优化。
Advantages
打造 SoC 的智能高效之选
10 倍设计效率提升
智能 NoC 自动生成技术使设计速度较传统 NoC 流程提升高达 10 倍，将 SoC 和芯粒系统的设计迭代周期从数周缩短至数天。
专家级设计成果
以最少的人工干预实现专家级 NoC 设计成果，在各种 NoC 项目中实现高达 3 倍的工程效率提升。智能算法可减少布线拥塞、优化芯片面积利用率，并与物理综合、布局及布线流程紧密协同，助力设计成功流片。
布线长度优化驱动性能提升
基于机器学习的智能 AI 算法可自动生成优化的 NoC 拓扑结构，实现平均布线长度缩短高达 30%，整体延迟降低高达 10%，并显著提升整个设计的能效表现。
芯粒就绪的 Multi-die 互连
FlexGen 裸片间控制器通过高度可配置的 FLIT 封装机制，实现 NoC 传输协议的高效跨裸片传输，在最大化 PHY 灵活性的同时降低带宽开销、延迟、面积和功耗，并支持 UCIe、BoW 等行业标准 PHY，助力高性能芯粒系统设计。
功能亮点
利用 FlexGen Multi-Die 实现 NoC 瓦格化
- 扩展系统性能
- 缩短设计周期
- 加速测试验证
- 降低设计风险
创建模块化、可扩展的设计，实现更快速的集成、验证和优化。
高效实现 SoC 内的数据移动
与 Arteris CodaCache® 末级缓存（Last-Level Cache, LLC） 的集成，进一步提升了系统创新能力：
- 适用于需要数据重复利用的数据密集型 NoC 应用
- 优化整体 SoC 的延迟与功耗表现
Efficient data movement through the SoC
NoC 集成自动化流程
借助 Arteris Magillem，通过自动化流程充分利用 SoC 连接信息：
- 精简设计流程，提升开发效率
- 通过检查器进行早期错误检测，提高设计质量
NoC integration automated flow
FlexGen Multi-Die 产品优势
专家级输出质量
自动生成智能 NoC 架构和物理约束，帮助设计团队以更少的人工投入获得高质量设计成果。
显著缩短布线长度
最大程度减少芯片面积、功耗和延迟。
10 倍生产力提升
通过自动化重复且耗时的任务，将设置与配置时间从数天缩短至数小时甚至数分钟，实现 10 倍生产力提升。
更高频率，更低延迟
利用内置的 NoC 性能分析与探索工具，优化系统性能，实现更高工作频率和更低通信延迟。
快速实现时序收敛
借助早期物理感知（Physical Awareness）能力，在无需重新设计的情况下实现更快的收敛。
自动化验证
与手动构建验证测试平台（Test Bench）相比，可节省数百小时的工作时间。
提升盈利能力
借助 FlexGen 带来的设计效率提升，缩短产品上市时间（Time-to-Market），从而提高盈利能力。
PHY 无关的 Die-to-Die 控制器
高度可配置的 FLIT（Flow Control Unit）格式 支持广泛的第三方行业标准 PHY IP，例如 UCIe、BoW 等。
产品对比表
| Category | Features | FlexWay | FlexNoC | FlexGen |
|---|---|---|---|---|
| Target Audience and Scale | Smaller-scale MCU SoCs | |||
| Small-medium scale SoCs | ||||
| Large scale SoCs | ||||
| Instances Per Design | Single NoC instance | |||
| Multiple NoC instances | ||||
| Network Interface Units (NIUs) per die¹ | Up to 50 NIUs | |||
| Up to 200 NIUs | ||||
| Up to 1000 NIUs | with XL option | with XL option | ||
| Up to 2000 NIUs | with 2XL option | |||
| Compatibility | AXI, AHB, APB, OCP, PIF, AMBA5 | |||
| ACE-Lite | ||||
| Smart NoC Automation | Topology generation with minimum wire length | |||
| Scripting-driven regular topology creation | ||||
| Incremental design capability | ||||
| Physical Awareness | Automatic timing closure assistance | |||
| Floorplan visualization | ||||
| Advanced Scalability | Enhanced Tiling2,3 | with XL options | with XL/2XL options | |
| Mesh topology editor | with XL options | with XL/2XL options | ||
| Write broadcast stations | with XL options | with XL/2XL options | ||
| Virtual channel links | with XL options | with XL/2XL options | ||
| Source synchronous asynchronous bridges | with XL options | with XL/2XL options | ||
| Up to 1024 bits data bus | with XL option | with XL option | ||
| Up to 2048 bits data bus | with 2XL option | |||
| 512 pending transaction support | with XL option | with XL option | ||
| 1024 pending transaction support | with 2XL option | |||
| Optimizations | Optimization for performance, area and wire length | |||
| Advanced Quality of Service (QoS) | ||||
| Power management and security | ||||
| Address and data protection schemes | ||||
| Advanced in-circuit debug features | ||||
| Multi-cycle SRAM support | ||||
| Floorplan visualization | ||||
| Add-on Options | Memory Re-order Buffer option | |||
| Reliability option | ||||
| Safety (up to ISO 26262 ASIL D) option | ||||
| Advanced Scalability (XL/2XL) options | ||||
| Markets | Automotive, Aerospace & Defence, Communications, Consumer Electronics, Enterprise Computing and Industrial Markets |
¹ NIU limits apply per individual monolithic die or chiplet design.
² FlexGen is advised for customers seeking to create a mesh topology using tiling.
³ Customers seeking to license multiple optional features should disclose its requirements to Arteris support engineers. Given the increasing complexity of designs, customers are advised to communicate their specific design needs to Arteris support engineers.
面向芯粒时代的 Multi-Die 解决方案
随着 AI 系统突破单裸片（Single-Die）限制并迈向 Multi-Die 架构，Arteris 始终保持系统架构的一致性，同时支持硅系统的持续扩展。
- 将智能 NoC 数据传输能力扩展至跨 Die 边界
- 保留 QoS、虚拟通道及原有设计意图
- 通过自动化技术和安全保障机制简化芯粒集成
Arteris Multi-Die 解决方案帮助工程团队将系统划分部署到多个 Die 之上，同时保持统一架构，缩短开发周期并降低集成风险。
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