Semiconductor Engineering: Interconnect Challenges Grow, Tools Lag
, 2020年06月15日
Interconnect Challenges Grow, Tools Lag
June 15th, 2020 – By Brian Bailey
More data, smaller devices are hitting the limits of current technology. The fix may be expensive.
Chips are growing. “Ten years ago, the interconnect would be concerned with about 10K gates,” says Benoit de Lescure, CTO for Arteris IP. “Now they need to interconnect 10M gates on a chip, so there’s been a very significant increase in complexity. The number of clients on the interconnect has increased.”
To read the entire SemiEngineering article, please click here: https://semiengineering.com/interconnect-challenges-grow-tools-lag/
