Semiconductor Engineering: Shortening Network-on-Chip Development Schedules Using Physical Awareness
, 2023年01月09日
Frank Schirrmeister, VP Solutions and Business Development at Arteris IP, authored this Semiconductor Engineering article:
January 5th, 2023 – By Frank Schirrmeister
Taking physical design into account as early as possible has been a consideration of chip development teams for quite some time. Still, in interactions with customers and partners, 2022 marked a sharp uptick in concerns about whether a design that may be functionally correct can also be implemented using physical implementation flows. Given the intricacies and complexity of network-on-chip (NoC) architectures and the dependencies on the size and placement of other IP blocks, they are susceptible to physical effects.
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